1. Field of the Invention
The present invention generally relates to a memory test circuit, and more specifically, to a parallel test circuit for selectively testing a desired specific bank as well as all banks in a parallel test on a semiconductor chip integrated on a silicon wafer and a parallel test method thereof.
2. Description of the Prior Art
When a test is performed on a semiconductor memory device, the test time is determined depending on the number of chips that can be test at one time. As a result, a parallel test method has been used because the test time can be reduced if the number of data input/output pins used in the test is decreased.
In the above-described parallel test method, data are written in all cells using a test code after entry of a test mode, and then defects of the chip are tested by compressing and reading each data.
FIG. 1 is a block diagram illustrating a read operation of a conventional parallel test method.
At a parallel test, 16 bit data of each bank B0˜B3 (EVEN/ODD) are compressed and outputted through corresponding one of data pads DQ2, DQ6, DQ9 and DQ13. Here, one bank is divided into half banks EVEN/ODD. Here, a low level signal is outputted if the chip is fail, and a high level signal is outputted if the chip is pass.
FIG. 2 is a circuit diagram illustrating a conventional parallel test circuit, and FIG. 3 is a circuit diagram illustrating a bank selecting unit 12, 14, 16 and 18 of FIG. 2.
The parallel test circuit of FIG. 2 comprises bank selecting units 12, 14, 16 and 18 which correspond one by one to banks. Each of the bank selecting units 12, 14, 16 and 18 selectively activates the corresponding bank in response to bank selecting control signals BA0, BA1 and a parallel test signal PTS.
In other words, each of the bank selecting units 12, 14, 16 and 18 selectively activates a desired bank in response to the bank selecting control signals BA0 and BA1 when the parallel test signal PTS is disabled to ‘low’. When the parallel test signal PTS is enabled to ‘high’, each of the bank selecting units 12, 14, 16 and 18 outputs bank selecting signals Out0˜Out3 as ‘low’ regardless of the bank selecting control signals BA0 and BA1 so that all the banks B0˜B3 may be selected at the same time.
Referring to FIG. 3, each of the bank selecting units 12, 14, 16 and 18 comprises PMOS transistors P1˜P3 and NMOS transistors N1˜N3. The PMOS transistors P1, P2 and the NMOS transistors N1, N2 are connected serially between a power voltage PWR terminal and a ground voltage GND terminal. Gates of the PMOS transistors P1 and P2 receive the parallel test signal PTS and the bank selecting control signal BA1, respectively. Gates of the NMOS transistors N1 and N2 receive the banks selecting control signals BA0 and BA1, respectively. The PMOS transistor P3 connected in parallel to the PMOS transistor P2 has a gate to receive the bank selecting signal BA0. The NMOS transistor N3 connected between an output terminal Out and the ground voltage GND terminal has a gate to receive the parallel test signal PTS.
FIG. 4 is a timing diagram illustrating data write and read operations in the conventional parallel test.
After a test mode register set signal TMRS for representing entry of the parallel test mode is applied, data applied through the data pads DQ2, DQ6, DQ9 and DQ13 are simultaneously written in all the banks B0˜B3 in response to a write signal. In response to a read signal, the data written in each bank B0˜B3 are respectively compressed and outputted through the data pads DQ2, DQ6, DQ9 and DQ13. That is, in the conventional parallel test circuit, data of the four banks are respectively outputted through one corresponding data pad at the same time.
As mentioned above, since all banks are simultaneously selected at the parallel test in the conventional parallel test circuit, only a specific bank cannot be selectively tested and the dependency on banks cannot be found in the wafer. Additionally, correlation of data cannot be found in comparison with other chips, either.